A typical computer system has at least a microprocessor and memory. The microprocessor processes, i.e., executes, instructions to accomplish various tasks of the computer system. Such instructions, along with the data required by the microprocessor when executing these instructions, are stored in some form of memory. FIG. 1 shows a typical computer system having a microprocessor (10) and some form of memory (20). The microprocessor (10) has, among other components, a central processing unit (also known and referred to as xe2x80x9cCPUxe2x80x9d or xe2x80x9cexecution unitxe2x80x9d) (12) and a memory controller (also known as xe2x80x9cload/store unitxe2x80x9d) (14). The CPU (12) is where the actual arithmetic and logical operations of the computer system take place. To facilitate the execution of operations by the CPU (12), the memory controller (14) provides the CPU (12) with necessary instructions and data from the memory (20). The memory controller (14) also stores information generated by the CPU (12) into the memory (20).
The operations that occur in a computer system, such as the logical operations in the CPU and the transfer of data between the CPU and memory, require power. If the components responsible for carrying out specific operations do not receive adequate power in a timely manner, computer system performance is susceptible to degradation. As an added challenge, power consumption of modern computers has increased as a consequence of increased operating frequencies. Thus, providing power to the components in a computer system in a sufficient and timely manner has become an issue of significant importance.
Often, power supplied to a computer system component varies, which, in turn, affects the integrity of the component""s output. Typically, this power variation results from the distance between a power supply for the component and the component itself. This distance may lead to the component not receiving power (via current) at the exact time it is required. One approach used by designers to combat this performance-inhibiting behavior is introducing decoupling capacitance (also referred to as xe2x80x9cdecapxe2x80x9d) to a particular circuit by positioning one or more decoupling capacitors close to the component. These decoupling capacitors store charge from the power supply and distribute the charge to the component when needed. For example, if power received by a component from a power supply attenuates, one or more decoupling capacitors will distribute charge to the component to ensure that the component is not affected by the power variation on the power supply. In essence, a decoupling capacitor acts as a local power supply for one or more specific components in a computer system.
Within a computer system component, such as a circuit, there are two types of decoupling capacitance: implicit and explicit. Explicit decoupling capacitance is provided to the circuit through the use of decoupling capacitors as discussed above. Implicit decoupling capacitance (also known in the art as xe2x80x9cparasitic capacitancexe2x80x9d or xe2x80x9cinherent capacitancexe2x80x9d) is capacitance that is inherent in a circuit. Implicit decoupling capacitance results from the electromagnetic effects between current-carrying wires. Further, implicit decoupling capacitance is a function of the distance between two such wires. Also, the ability to help supplement an attenuating voltage using explicit decoupling capacitors or implicit decoupling capacitance is a function of the potential applied to the decaps.
FIG. 2 shows the presence of explicit and implicit decoupling capacitance in a section of a typical computer system component (40). The component (40) has a power supply bus (44) and a ground bus (46) that provides power through a connection to a power supply (42). The power supply (42) may be a part of the component (40) or a separate element. Power from the power supply (42) is made available to multiple power supply lines (48) and (52) via connections to the power supply bus (44) and to multiple ground lines (50) and (54) via connections to the ground bus (46). Power from the power supply (42) is delivered to chip logic circuits (60) and (68) via the power supply lines (48) and (52), respectively, and ground lines (50) and (54), respectively. When there is power variation across the power supply (42), explicit decoupling capacitors (56), (57), (58), and (59) positioned in parallel with the power supply (42) provides charge, i.e., power, to the chip logic circuits (60) and (68).
Still referring to FIG. 2, the existence of implicit decoupling capacitances (64), (66), (72), and (74) is shown. A first occurrence of implicit decoupling capacitance (64) occurs between the power supply line (48) and a signal line (62) from the chip logic (60). A second occurrence of implicit decoupling capacitance (66) occurs between the signal line (62) and the ground line (50). The implicit decoupling capacitances (64) and (66) are dependent on the characteristics of the signal line (62), specifically, whether a signal on the signal line (62) is high or low. When the signal is low, the implicit decoupling capacitance provided to the chip logic (60) is equal to the implicit decoupling capacitance (64) between the power supply line (48) and the signal line (62). Alternatively, when the signal is high, the implicit decoupling capacitance provided to the chip logic (60) is equal to the implicit decoupling capacitance (66) between the signal line (62) and the ground line (50).
Still referring to FIG. 2, implicit decoupling capacitance is also present in a substantial number of additional circuits. For example, another first occurrence of implicit decoupling capacitance (72) occurs between the power supply line (52) and a signal line (70) from the chip logic (68). Another second occurrence of implicit decoupling capacitance (74) occurs between the signal line (70) and the ground line (54). The implicit decoupling capacitances (72) and (74) are dependent on the characteristics of the signal line (70), specifically, whether a signal on the signal line (70) is high or low. When the signal is low, the implicit decoupling capacitance provided to the chip logic (68) is equal to the implicit decoupling capacitance (72) between the power supply line (52) and the signal line (70). Alternatively, when the signal is high, the implicit decoupling capacitance provided to the chip logic (68) is equal to the implicit decoupling capacitance (74) between the signal line (70) and the ground line (54).
With reference to FIG. 2, one of ordinary skill in the art will understand that even with a limited number of logic circuits (60, 68), the number of connecting lines, including power supply lines (48, 52), ground lines (50, 54), and signal lines (62, 70), is numerous. As the number of logic circuits increase, generally, the number of connecting lines increase accordingly. To manage the proper connection of power, ground, and/or signal lines, a program, often called a xe2x80x9crouting programxe2x80x9d or xe2x80x9crouterxe2x80x9d, is executed on a computer to route the connections.
A database is used to maintain information necessary for the manufacture of an integrated circuit. The locations of the logic circuits, along with their connections to other circuits, form some of the information contained in the database. A routing program, often using a set of rules, is responsible for making the appropriate connections between elements on the integrated circuit. The set of rules varies, but may include, among other things, which signals are routed first, locations where a signal may or may not be routed, whether the signals must stay on a grid or can be freeform, width of the signal lines, spacing between signal lines, and which layers are allowed to be used in a multilayer connection arrangement.
According to one aspect of the present invention, a method for preferentially shielding a signal path having a value switchable between a first potential and a second potential comprises determining a probability of the value being at the first potential versus the second potential, assigning a third potential to a first plurality of shields, assigning a fourth potential to a second plurality of shields, defining a plurality of possible routing channels among the first plurality of shields and the second plurality of shields, and assigning the signal path to one of the plurality of possible routing channels depending on a relationship among the probability, the third potential and the fourth potential.
According to another aspect, an integrated circuit comprises a signal having a value switchable between a first potential and a second potential, the value having a probability of being at the first potential versus the second potential; a first plurality of shields at a third potential; and a second plurality of shields at a fourth potential where the signal is routed along one of a plurality of possible routing channels among the first plurality of shields and the second plurality of shields, and where one of the plurality of possible routing channels is selected based upon a relationship among the probability, the third potential and the fourth potential.
According to another aspect, a computer system for preferentially routing a signal having a value switchable between a first potential and a second potential on an integrated circuit comprises a processor, a memory, and software instructions stored in the memory for enabling the computer system under control of the processor for determining a probability of the value being at the first potential versus the second potential, assigning a third potential to a first plurality of shields, assigning a fourth potential to a second plurality of shields, defining a plurality of possible routing channels among the first plurality of shields and the second plurality of shields, and assigning the signal to one of the plurality of possible routing channels depending on a relationship among the probability, the third potential and the fourth potential.
According to another aspect, a computer-readable medium having recorded thereon instructions executable by a processor, where the instructions are for determining a probability of a signal value being at a first potential versus a second potential, determining a third potential of a first plurality of shields, determining a fourth potential of a second plurality of shields, identifying a plurality of possible routing channels among the first plurality of shields and the second plurality of shields, and assigning the signal to one of the plurality of possible routing channels depending on a relationship among the probability, the third potential and the fourth potential.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.